Parameters that limit the performance of analog to digital converters (A/D) are, the maximum digitizing rate, the effective aperture width of the samples, and the settling time of comparators. Although it is easy to extend the digitizing rate by multiplexing several A/D converters in time, this does not remove the requirements on speed which are imposed by the bandwidth of the signal being digitized.
The two most popular at the present time are: the successive approximation type, and the parallel or flash converter type, the half-flash converter, which combines both successive approximation and flash methods. In a successive approximation converter, a voltage is generated from zero to maximum, by an internal digital-to-analog converter and each successive increment compared with the converter input voltage until a match is reached, the setting of the DA converter then represents the value of the input voltage. A flash converter consists essentially of a voltage divider resistor ladder with fixed tap positions defining resistor segments corresponding to the desired resolution of the converter. Accordingly, a converter of "n" bit resolution would require 2.sup.n+1 resistor segments. Each tap is connected to a comparator of its own, and accordingly 2.sup.n-1 comparators are needed. Each comparator compares its voltage divider voltage with the converter's input voltage. The line of comparators respond according to a "thermometer code", those comparators with thresholds below the converter input voltage, turn on, while those with thresholds above the input voltage remain off. The output of all the comparators is then translated by an encoder into a binary or decimal number. A typical commercial flash computer is Honeywell, Inc.'s HADC 77100 flash A/D converter. In a half-flash converter, the output of a first flash-converter of low resolution is sued to generate a voltage by means of an internal digital-to-analog converter, this voltage is then subtracted from the input voltage to provide a new voltage representing the lower resolution portion of the input voltage, which is then fed into a second flash-converter unit and both results combined by appropriate encoder units. Here speed is sacrificed for reduction in total number of comparators, however the total circuit is no longer monotonic. It can be seen that typically a successive approximation method is very slow as it does require 2.sup.n-1 successive operations, and a flash-converter is complex as it requires 2.sup.n-1 comparators. By way of example, an 8 bit converter would require 255 comparators, since it increases geometrically. See Krynicki U.S. Pat. No. 4,571,574 from which the preceding was taken. In some commercial flash converter units there is a decreasing performance with increase in bandwidth. Covitt U.S. Pat. No. 4,168,470 discloses a two bit A/D converter in which the input analog signal is supplied to a pair of channels, each channel having a modulator, a low pass filter and a full wave rectifier in each channel to supply a pair of A/D converters to provide a two bit A/D converter. In Konig et al. U.S. Pat. No. 4,611,194 an analog data pulse is applied in parallel to plurality of low speed A/D converters and to one or more level detectors, each of which has a preset threshold so that when the signal crosses the reference threshold a strobe is produced and applied to a delay circuit which then applies the strobe (after a predetermined delay) to its related A/D converter. The A/D converters sample the analog data in response to its associated delayed strobe to provide a digital value of the sample. The A/D digital outputs are multiplexed and compared to produce the output.
The basic objective of this invention is to provide an improved wide bandwidth A/D converter. A further object of this invention is to provide a method and apparatus for making it possible to multiply the digitizing rate of an A/D by an integer and at the same time to reduce the requirements upon the speed of the A/D converters by the same integer. The A/D converter according to this invention automatically demultiplexes the high speed digital samples into several low speed channels for recording or analysis. A further feature of the invention is that balanced modulators are not required because the bandwidths of the low pass filters reject the sum and products and modulation frequencies.